1. Field of the Invention
This invention relates to a semiconductor integrated circuit and a redundancy method thereof and, for example, to a redundancy method of a semiconductor integrated circuit having a memory macro buried therein or a system containing the memory macro.
2. Description of the Related Art
In a semiconductor integrated circuit, a buried memory macro (memory device) is designed with the finest dimensions and is a portion in which physical defects tend to occur in the manufacturing process. Since the memory macro is formed to have a regular pattern, a defective portion can be easily specified than in a random logical portion. Further, the redundancy relieving technique of relieving the defective portions by means of a redundancy configuration and shipping the integrated circuit in a good state is generally used. Since the defective portions to be relived are different for each integrated circuit manufactured, repair position information must be provided for each integrated circuit. In order to store the information, a fuse device that can be programmed only once or a rewritable nonvolatile memory device is used.
It is necessary to provide plural bits for the repair position information for each memory macro and the bit number thereof becomes different depending on the type of the memory macro and the configuration of word number, bit width and the like. For example, in the simplest case, the configuration can be attained by providing a storage device that can store the required number of bits on the integrated circuit. However, in the actual manufacturing process, the number of memory macros having defects is extremely smaller in comparison with the total number of memory macros and, for example, one to three devices among several hundred devices in total are provided in many cases. Therefore, it is uneconomical from the viewpoint of area cost to provide a repair position information storage device on the integrated circuit on the assumption that all of the memory macros can be relieved.
In order to solve the above problem, a configuration of providing the repair position information and device recognition information used to determine a memory macro to which the repair position information corresponds is proposed so as to reduce the required number of storage bits in the storage device. With this configuration, the size of the storage device required for each memory macro is increased. However, since it is only required to store information indicating only the number of repair information items estimated as the maximum required number, the number of information items can be remarkably reduced in comparison with a case wherein information items for all of the memory macros are stored.
In this case, several variations of a method for giving data to a memory macro to be actually relieved based on the reduced number of stored information items are considered. For example, basically, the configuration of providing repair information required only for a corresponding memory macro based on a memory macro identification information portion of the storage information becomes necessary. For example, the configuration is considered in which a decode circuit is provided in the output portion of a repair information storage device, desired repair information is supplied to a memory macro indicated by device identification information and non-repair information is supplied to other memory macros free from defects. Data can be transferred from the repair information storage device to the memory macro in parallel or in series. However, with the above configuration, if the number of memory macros (memory devices) or the configuration of the memory macro is changed, there occurs a problem that the decode circuit must be reconfigured.
As the configuration of solving the above problem, for example, the configuration in which repair information analyzing circuits are provided in respective memory macros (memory devices) is proposed. With this configuration, even if the number of memory macros or the configuration of the memory macro is changed, it is only required to add or omit a repair information analyzing circuit. Therefore, even if the number of memory macros or the configuration of the memory macro is changed, it is not necessary to reconfigure the decode circuit.
However, with the above configuration, it is necessary to repeatedly transfer repair information plural times for respective memory macros when the number of bits of the repair information of each memory macro is different. Therefore, for example, clocks corresponding to the different numbers of bits are further required to transfer unit repair information items and unit repair information is required to be repeatedly transferred plural times corresponding to the number of unit repair information items to be transferred as the whole system.
There is also provided a method for transferring unit repair information via a bus (for example, see Jpn. Pat. Appln. KOKAI Publication No. 2003-85994). However, with this method, interconnections in the chip become complicated and the control operation of fetching data from the bus becomes complicated when the number of memory macros is large.